I2C is widely adopted in the semiconductor industry. For a successful inter-operation of different ICs using I2C bus, there should be compatibility in electrical characteristics of physical layer signals of I2C SCL and SDA signals. The timing between the master and slave devices should be within electrical specifications defined in I2C Specification by NXP Semiconductor.
fSCL – Clock frequency: Inverse of one cycle period measured at 30% of amplitude of SCL signal. It should be measured at first cycle of after the START condition.
tr - Rise time of the SCL and SDA signals: time taken by rising edge to reach 70% of the amplitude from 30% of the amplitude of SCL and SDA signals.
tf – Fall time of the SCL and SDA signals: time taken by the falling edge of the signals to reach 30% of the amplitude from 70% of the amplitude of SCL and SDA signals
tHD;STA Hold time (repeated) START condition: Minimum time the data should be low before SCL is in low state at (repeated) START condition. It is measured as time taken from 30% of the amplitude of SDA at high to low transition to 70% of the amplitude at high to low transition of SCL Signal.
tLOW Low period of the SCL: It is minimum low time should be maintained by SCL signal. It is measured as half period measured at 30% of the amplitude of the SCL signal.
tHIGH High period of the SCL: It is minimum high time should be maintained by SCL signal. It is measured as half period measured at 70% of the amplitude of SCL signal.
tSU; STO Setup time at STOP condition: It is measured at STOP condition of I2C frame. It is measured as time between 70% of the amplitude at rising edge of SCL signal to 30% of the amplitude of SDA signal at STOP condition.
tSU;STA Setup time forrepeated START condition: This measurement is carried out at repeated START condition only. It is time measured between SCL and SDA signal at 70% amplitude of the signals.
tVD; DAT Data Valid time: Measured at every data and clock transition. This is measured with reference to 30% amplitude falling edge of SCL to 70% of rising edge or 30% of the falling edge of SDA signal. The I2C specification maximum allowed data valid time at different I2C speeds.
tVD; ACK Data valid acknowledge time: Measured at acknowledgement bit. It is time from 30% of falling edge of eighth clock from start of data to 70% of the ack bit or 30% of the ACK bit.
It is essential to validate all the above parameters of the I2C device for the successful interoperation of IC using I2C bus.
The PGY-I2C Electrical Validation and Protocol Decode Software captures the I2C waveforms using Tektronix DPO/MSO/DSA 70000, TDS7000B, DPO5000 Oscilloscope and provides simple pass/ Fail resultsall the I2C electrical measurements every possible I2C protocol state and displays the min, max and mean values.
More details on PGY-I2C can be found at: PGY-I2C Electrical Validation and Protocol Decode Software
Applications of I2C
SMBus (System Management Bus) is a derivative of I2C bus used for managing the communication between computer mother board to power sources, defined by Intel in 1995.
The Power Management Bus (PMBus) is an another varient of I2C bus, which is targeted at digital management of power supplies. Like SMBus, it is a relatively slow speed two wire communications protocol based on I²C.
HDMI’s Display Data Channel (DDC) is a communication channel based on the I²C bus. DDC channel is used for source device to read the E-EDID data from the HDMI sink device to learn what audio/video formats it supports. The DDC bus is also used to exchange the secret keys for encryption are exchanged between the source and display over an I2C bus.
PGY-I2C Electrical Validation and Protocol Decode Software