• Responsibilities
  As a Sr. Engineering will be working on our existing and next generation Protocol Analyzers and exercisers and similar products.
• Manages the FPGA and Board design team.
• Develop a new products to meet needs top semiconductor for their pre and post silicon validation.
• The role involves contributing to the entire FPGA based product development flow starting from requirement analysis till final product testing in lab environment.
• The candidate will be responsible for architecture/micro-architecture design and implementation of the logic in
• Verilog for targeted FPGA, writing test benches to validate the design etc.
• Job involves working with team of FPGA Design Engineers and deliver the products as planned.
• Guides the team to Debugging of designs to resolve complex design issues.
• Job involves frequent interaction with board design, software, testing and lab teams to deliver the product meeting the customer requirements.
• Job involves understanding and working with interfaces such as PCIe, GigE, MPHY/UFS, DPHY/CSI/DSI, USB, SD, eMMC, I3C/I2C, SPI/QSPI etc.
• Contributing to/participating in internal design reviews to ensure adherence to the company FPGA design process.
• Maintaining all design documents and code base in SVN.
• Participate and contribute to the standard bodies such as PCIeSig, MIPI Alliance, SD Association, and USB Org.
• Owns responsibility filing patents.
• International travel is involved.

Qualifications

• BE/ME in Electronics from a reputed college. Specialization in VLSI and Embedded Design is a plus.
• 12 to 15 years of experience in designing and implementing FPGA-based solution in Xilinx or Altera FPGA, preferably FPGA-based product development experience.
• Knowledgeable in board design.
• Must have experience in System Design with Xilinx/Altera FPGA devices with relevant tools.
• Deep expertise in FPGA-based data plane design to manage the high-speed serial bus data.
• Must have experience in Verilog and/or VHDL coding.
• Must have very good understanding of physical layer of SERDES of XILINX-AMD or Intel FPGA.