PCIe Protocol Analyzer
The industry-leading PCIe test instrument for capturing, decoding, and debugging PCIe Gen1 through Gen5 designs. Supports 2.5, 5, 8, 16, and 32 GT/s with complete TLP, DLLP, and LTSSM analysis at an affordable price.
PCIe
PCI Express (PCIe) is the dominant high-speed serial interconnect standard for connecting processors, GPUs, NVMe SSDs, and peripheral devices inside modern computing systems. From Gen1 to Gen5, PCIe has doubled bandwidth with each generation - reaching 32 GT/s per lane at Gen5, delivering up to 128 GB/s in an x16 configuration.
The PGY-PCIeGen3/4/5-PA supports protocol analysis across all PCIe generations from Gen1 to Gen5, capturing and recording traces at 2.5, 5, 8, 16, and 32 GT/s. PCIe data is captured using interposers placed between the Root Complex and the Endpoint (Device Under Test), enabling non-intrusive analysis of all bus activity.
Why a Protocol Analyzer? PCIe link bring-up, LTSSM state machine behaviour, TLP/DLLP errors, and NVMe command flows are nearly impossible to debug with oscilloscopes alone. A protocol analyzer captures and decodes every packet in real time - giving engineers instant visibility into protocol-level faults that would otherwise take days to isolate.
Key Features
- PCIe Gen1/2/3/4/5 Protocol Decode & Analysis - x4 and x8 lane configurations
- Protocol Decoding of TS1, TS2, TLP, DLLP, SDS, IDLE, EIOS, EIEOS, FTS, SKP packets
- Hardware-based protocol packet filter capabilities (TS1, TS2, IDLE)
- Software-based search, filter-in, and filter-out capabilities
- Standard 16 GB trace buffer - expandable to 64 GB combined TX and RX
- Continuous streaming of protocol data to host computer SSD/HDD
- Detailed view of every TLP/DLLP with all field values decoded
- Trigger-out signal at trigger event for synchronising oscilloscopes and other instruments
- Decoded data packets can be exported to .txt for further analysis
- Field-upgradeable firmware - remote upgrade to the latest feature set
- Lightweight and portable - suitable for on-site and field deployments
- Host interface via USB 3.0
NVMe Protocol Decode
The PGY-PCIeGen3/4/5-PA includes NVMe Protocol Decode capabilities alongside full PCIe layer analysis. Engineers can inspect NVMe command queues, completion entries, and configuration registers directly within the decode view - without needing a separate tool.
- NVMe command and completion queue decode over PCIe TLP layer
- Configuration Register decode: Device/Vendor ID, BAR, Capabilities, Link Control/Status
- Correlation between NVMe commands and underlying PCIe TLP transactions
- Filter-in on NVMe-specific TLP patterns for targeted debug
LTSSM Analysis
The Link Training and Status State Machine (LTSSM) governs PCIe link initialisation and power management. The PGY-PCIeGen3/4/5-PA provides a dedicated LTSSM view that displays upstream and downstream state transitions in real time, correlated to the captured protocol traffic.
- Real-time LTSSM state machine view for upstream and downstream directions
- State transition timestamps correlated to TLP/DLLP capture timeline
- TS1/TS2 ordered set decode during Polling and Configuration states
- Recovery state entry detection - ideal for diagnosing link instability at Gen4/Gen5 speeds
Trigger Capabilities
Auto, simple, and advanced multi-level if-then-else trigger conditions based on TS1, TS2, TLP, and DLLP packet contents.
Immediately starts capture on any PCIe bus activity. Ideal for initial exploration of an unknown DUT or link behaviour.
Trigger on a specific protocol event - TS1, TS2, TLP type, DLLP type, or packet field value. Captures pre- and post-trigger data windows around the event of interest.
Multi-level if-then-else-if trigger conditions monitoring multiple simultaneous conditions across TS1, TS2, TLP, and DLLP packet contents.
- Multi-state trigger sequencing with configurable conditions per state
- Trigger on TLP type, address range, tag, requester/completer ID, status
- Trigger on DLLP type, sequence number, CRC errors
- Trigger-out BNC signal for oscilloscope synchronisation
Prodigy Interposers
PCIe data is captured non-intrusively using interposers placed between the Root Complex and Endpoint. The M.2 interposer is included as standard. Additional interposers are available as optional accessories.
PGY-INT-M.2 - Standard interposer shipped with every analyzer. Supports M.2 form-factor NVMe SSDs and Wi-Fi cards at PCIe Gen1 through Gen5 speeds.
PGY-INT-CEM (Opt.CEM8 / Opt.CEM4) - CEM X8 and X4 interposers for standard PCIe add-in cards such as graphics cards, accelerators, and RAID controllers.
PGY-INT-U.2 (Opt.U2) - U.2 X4 interposer for enterprise NVMe drives in U.2 (SFF-8639) form factor. Supports PCIe Gen1 through Gen5.
Opt.E1.S - Interposer for E1.S (EDSFF) form-factor NVMe SSDs used in high-density data centre storage platforms.
PGY-INT-SDX (Opt.SDX) - Interposer for SD Express cards which use PCIe Gen3 x1 over the SD card interface. Connects via USB 3.2 cable and USB-to-SDX adapter.
Product Comparison
Three configurations - Gen3, Gen4, and Gen5 - each supporting all lower generations. Choose the model that matches your highest target PCIe generation.
- PCIe Gen1 / Gen2 / Gen3
- Up to 8 GT/s per lane
- TLP / DLLP / LTSSM Decode
- 16 GB Trace Buffer
- M.2 Interposer Included
- Solder Down Active Probes (Optional)
- Gen4 (16 GT/s)
- Gen5 (32 GT/s)
- PCIe Gen1 / Gen2 / Gen3 / Gen4
- Up to 16 GT/s per lane
- TLP / DLLP / LTSSM Decode
- 16 GB Trace Buffer (up to 64 GB)
- M.2 Interposer Included
- NVMe Protocol Decode
- Advanced Multi-Level Triggers
- Gen5 (32 GT/s)
- PCIe Gen1 / Gen2 / Gen3 / Gen4 / Gen5
- Up to 32 GT/s per lane
- TLP / DLLP / LTSSM Decode
- 16 GB Trace Buffer (up to 64 GB)
- M.2 Interposer Included
- NVMe Protocol Decode
- Advanced Multi-Level Triggers
- Trigger-Out for Oscilloscope Sync
| Feature | PGY-PCIeGen3-PA Gen3 Analyzer | PGY-PCIeGen4-PA Gen4 Analyzer | PGY-PCIeGen5-PA Gen5 Analyzer |
|---|---|---|---|
| PCIe Gen1 (2.5 GT/s) | ✓ | ✓ | ✓ |
| PCIe Gen2 (5.0 GT/s) | ✓ | ✓ | ✓ |
| PCIe Gen3 (8 GT/s) | ✓ | ✓ | ✓ |
| PCIe Gen4 (16 GT/s) | – | ✓ | ✓ |
| PCIe Gen5 (32 GT/s) | – | – | ✓ |
| TLP / DLLP Decode | ✓ | ✓ | ✓ |
| LTSSM Analysis | ✓ | ✓ | ✓ |
| NVMe Protocol Decode | – | ✓ | ✓ |
| Config Register Decode | – | ✓ | ✓ |
| Advanced Multi-Level Trigger | – | ✓ | ✓ |
| Trigger-Out Signal | – | ✓ | ✓ |
| Trace Buffer | 16 GB | Up to 64 GB | Up to 64 GB |
| Host Interface | USB 3.0 | USB 3.0 | USB 3.0 |
| Operating System | Win 8/10/11 | Win 8/10/11 | Win 8/10/11 |
Specifications
Ordering Information
Datasheets, Videos & Blogs
