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Protocol Analyzers / I3C / PGY-I3C-EX-PD
PGY-I3C-EX-PD

I3C Protocol Exerciser
&Analyzer

The industry-leading MIPI I3C test instrument for capturing, validating, and debugging I3C designs. Operate as Controller, Target, or Secondary Controller with full support for higher-level protocols including NVMe-MI, MCTP, SPDM, and PLDM over I3C.

PGY-I3C-EX-PD I3C Protocol Analyzer and Exerciser
SDR/HDR Modes
12.5MHz Max Freq
I3C v1.1 Standard

I3C

MIPI I3C (Improved Inter Integrated Circuit) is a high-speed, low-power serial interface standard developed by the MIPI Alliance as the next-generation successor to I2C. It was designed to unify and replace the fragmented sensor interface landscape - combining the simplicity of I2C with speeds approaching SPI, while reducing pin count and power consumption significantly.

I3C operates over a two-wire bus (SCL and SDA) and supports multiple operating modes: Single Data Rate (SDR) at up to 12.5 MHz and High Data Rate (HDR) modes including HDR-DDR (up to 25 Mbps) and HDR-TSP/TSL (33 Mbps). A defining feature of I3C is its support for In-Band Interrupts (IBI) - devices can interrupt the Controller on the data line without requiring dedicated interrupt pins.

Why I3C? I3C achieves up to 12.5x the throughput of standard I2C while using the same two-wire topology, eliminating the need for dedicated interrupt lines and enabling dynamic address assignment, hot-join, and controllership handoff - all critical for modern sensor-dense systems.

Key I3C Features Supported

  • SDR and HDR (DDR, TSP, TSL) transfer modes
  • Dynamic Address Assignment (DAA) - ENTDAA, SETDASA, SETAASA
  • In-Band Interrupts (IBI), Hot-Join, and Controllership Request
  • Broadcast and Directed Common Command Codes (CCC)
  • Bus configuration support: 1 Controller + 3 Targets or 1 Controller + 1 Secondary Controller + 2 Targets
  • Legacy I2C device compatibility on the same bus (FM, FM+, UFM)
  • Full MIPI I3C v1.0, v1.1, v1.1.1, and v1.2 specification compliance
  • Error injection: CRC, Parity, ACK/NACK, Preamble Errors and timing faults

Analyzer & Exerciser Functionality

The PGY-I3C-EX-PD can operate simultaneously as an Analyzer and Exerciser. In exerciser mode, it generates I3C traffic - configurable Controller, Secondary Controller, or Target - allowing engineers to validate DUT behavior without needing a separate traffic source. In analyzer mode, it passively captures and decodes all I3C bus activity in real time, displaying waveforms, protocol listings, and state machine transitions in a unified GUI.

  • Script-based exerciser with Python and C++ API for automation
  • Auto, Simple, and Advanced (multi-state) hardware trigger modes
  • Continuous protocol data streaming to host PC via USB 2.0 / USB 3.0
  • Timing diagram with SCL/SDA overlay, protocol listing, and state machine views
  • Margin testing: voltage and timing variation for robustness validation
I3C Analyzer and Exerciser Functionality screenshot

Higher Level Applications over I3C

I3C has evolved beyond simple sensor connectivity. Modern system architectures run complex management and security protocols over the I3C physical layer, enabling rich device management, security attestation, and firmware update capabilities through a single two-wire interface. The PGY-I3C-EX-PD provides full decode and exerciser support for all major higher-level protocols transported over I3C.

MCTP OVER I3C

Management Component Transport Protocol (MCTP) is a DMTF standard that provides a message-passing transport layer for platform management communications. Running MCTP over I3C (MCTP-I3C, DSP0233) enables low-cost, low-power platform management for server BMC subsystems, replacing dedicated SMBus/I2C management channels.

The PGY-I3C-EX-PD provides complete MCTP over I3C decode including message type identification, endpoint addressing, packet assembly across multi-packet messages, and error detection. An optional MCTP exerciser generates MCTP traffic over the I3C physical layer for endpoint validation.

  • MCTP baseline message types: Control, NVMe-MI, PLDM, SPDM
  • Multi-packet message reassembly and sequence tracking
  • MCTP over I3C transport binding per DMTF DSP0233
  • Endpoint discovery and routing table display
MCTP over I3C screenshot
NVMe-MI OVER I3C

NVM Express Management Interface (NVMe-MI) defines a management interface for NVMe subsystems. When transported over I3C, NVMe-MI enables out-of-band management of storage devices - including health monitoring, firmware update, and configuration - without requiring a separate management network or PCIe link.

The PGY-I3C-EX-PD decodes NVMe-MI commands and responses over I3C, displaying command type, controller ID, response status, and payload data in the protocol listing view. The exerciser can generate NVMe-MI transactions for DUT validation.

  • Full NVMe-MI command decode: Controller Health Status, Read NVMe-MI DS, Configuration Get/Set and Admin command support
  • NVMe-MI over SMBus/MCTP tunneling decode
  • Exerciser: generate NVMe-MI management commands over I3C transport
NVMe-MI over I3C screenshot
SPDM OVER I3C

Security Protocol and Data Model (SPDM) is a DMTF standard that enables authentication, attestation, and secure session establishment between platform components. SPDM over I3C is increasingly used in server platforms to verify the identity and firmware integrity of attached devices, from storage controllers to accelerators.

The analyzer decodes SPDM message exchanges over I3C/MCTP transport - displaying GET_VERSION, GET_CAPABILITIES, NEGOTIATE_ALGORITHMS, GET_DIGESTS, GET_CERTIFICATE, CHALLENGE, and MEASUREMENTS sequences in the protocol listing with full payload decode.

  • SPDM v1.0, v1.1, v1.2 message decode
  • Certificate chain extraction and certificate field parsing
  • Measurement block decode for firmware attestation verification
  • Session establishment and key exchange decode
SPDM over I3C screenshot
PLDM OVER I3C

Platform Level Data Model (PLDM) is a DMTF standard that standardizes data formats for platform management information including sensors, FRU data, firmware update, and BIOS/UEFI configuration. PLDM over MCTP over I3C creates a complete, unified management stack on the two-wire bus.

The PGY-I3C-EX-PD decodes PLDM messages across all defined message types, enabling engineers to verify that firmware update sequences, sensor polling, and event notification flows are correctly implemented by the DUT.

  • PLDM base messaging control and discovery commands
PLDM over I3C screenshot

Conformance Test Suite (CTS)

I3C Conformance Test Suite CTS

The PGY-I3C-EX-PD is a comprehensive I3C exerciser and protocol analyzer designed for engineers developing and validating devices against the MIPI I3C v1.2 specifications. Combining Controller and Target emulation, real-time traffic capture, decode, and a fully integrated Conformance Test Suite, it delivers everything needed for functional validation, debug, and compliance testing - in a single standalone instrument with no external tools required.

  • Protocol support: MIPI I3C v1.0, v1.1, v1.1.1, and v1.2
  • Transfer modes: SDR, HDR-DDR, HDR-TSP, HDR-TSL, HDR-BT
  • Emulation: Primary Controller and Target roles
  • CTS: 44 Controller + 56 Target automated test cases
  • Standalone operation - no external instruments or software dependencies
  • Fully integrated GUI for exerciser, analyzer, CTS, and reporting workflows
I3C CTS overview screenshot
MCTP Conformance Test Suite CTS

The MCTP CTS validates that a DUT correctly implements the MCTP specification (DMTF DSP0236) and the MCTP over I3C transport binding (DMTF DSP0233). Tests cover endpoint discovery, message routing, fragmentation and reassembly, error handling, and timing requirements.

  • Automated MCTP endpoint discovery and enumeration tests
  • Message fragmentation, reassembly, and sequence number validation
  • MCTP control command compliance: Set/Get Endpoint ID, Get Message Type Support
  • Transport binding compliance for I3C per DSP0233
  • Error injection and negative testing for robustness validation
  • Structured test report generation with pass/fail/warning classification
MCTP CTS screenshot
NVMe-MI Conformance Test Suite CTS

The NVMe-MI CTS validates compliance with the NVMe Management Interface specification. Tests are organized across the NVMe-MI command set to verify correct command handling, response format, status codes, and error behavior in the DUT.

  • NVMe-MI Controller Health Status Poll (CHSP) command tests
  • Read NVMe-MI Data Structure tests: Controller List, Controller Information, Opt Supp Cmd List
  • NVMe-MI Configuration Get and Set command validation
  • VPD Read/Write command tests
  • Error response validation: invalid commands, out-of-range parameters
  • Timing and response latency compliance tests
NVMe-MI CTS screenshot
SPDM Conformance Test Suite CTS

The SPDM CTS validates DMTF SPDM specification compliance across the full authentication and attestation flow. Tests are sequenced to mirror real device interaction flows - from capability negotiation through certificate exchange to measurement retrieval and session establishment.

  • Version negotiation tests: GET_VERSION / VERSION exchange validation
  • Capability negotiation: GET_CAPABILITIES / CAPABILITIES compliance
  • Algorithm negotiation: NEGOTIATE_ALGORITHMS coverage across required suites
  • Certificate chain validation: GET_DIGESTS, GET_CERTIFICATE, chain format tests
  • Authentication tests: CHALLENGE / CHALLENGE_AUTH with multiple hash algorithms
  • Measurement tests: GET_MEASUREMENTS for firmware attestation compliance
  • Negative tests: invalid request handling, replay attack detection
SPDM CTS screenshot

HDR-BT (Bulk Transfer)

HDR-BT BULK TRANSFER

PGY-I3C-EXPD enables deep validation and debug of HDR Bulk Transfer (HDR-BT) mode, delivering high-throughput, efficient, and reliable data communication over I3C.

  • HDR-BT frame decoding and visualization
  • Burst-level analytics (length, gaps, efficiency)
  • Protocol-aware triggering for HDR events
  • Timing correlation between SDR and HDR modes
  • High-speed capture without data loss
  • Error and anomaly detection in burst transfers

Multi-Lane

Multi-Lane M-LANE

PGY-I3C-EXPD enables validation and debug of emerging multi-lane I3C architectures, delivering higher bandwidth, parallel data transfer visibility, and future-ready compliance support.

  • Multi-lane data capture and decoding
  • Lane-wise and aggregated data analysis
  • Cross-lane timing correlation
  • High-speed buffering for large data bursts
  • Protocol-aware triggering across lanes
Multi-Lane I3C screenshot

Product Portfolio

Prodigy Technovations offers the PGY-I3C-EX-PD in multiple configurations to match your validation requirements - from basic I3C protocol capture to a full-featured exerciser with CTS compliance testing and higher-level protocol support.

I3C Exerciser & Analyzer-Lite
PGY-I3C-EX-PD
Lite
  • I3C SDR Protocol Capture
  • Protocol Listing & Decode GUI
  • Trigger: Auto & Simple
  • USB 3.0 Interface
16 Digital Channel I3C Logic Analyzer
PGY-LA-EMBD
Analyzer
  • I3C Protocol decode analysis
  • I3C Protocol aware trigger
  • System design support
  • Cost-effective solution – $1,950
I3C Exerciser + CTS Suite
PGY-I3C-EX--PD
Full Suite
  • All PGY-I3C-EX-PD features
  • MIPI I3C CTS v1.1.1 (90+ tests)
  • MCTP CTS Test Suite
  • NVMe-MI CTS Test Suite
  • SPDM CTS Test Suite
  • Automated report generation
  • PLDM Exerciser & Analyzer
I3C USB Adapter
PGY-I3C_USB
I3C USB Adapter
  • Comprehensive Production Test solution
  • Supports CCC and operation upto 12.5 MHz
  • Fixed Voltage Level for Reliable testing
  • Seemless Integration for Efficient Testing Process

Ready to Validate Your I3C Design?

Request pricing, evaluation units, or schedule a product demonstration of the PGY-I3C-EX-PD.