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Protocol Exercisers & Analyzers

I3C Protocol Exerciser and Analyzer

Model No: PGY-I3C-EX-PD

The I3C Protocol Analyzer (PGY-I3C-EX-PD) is the leading instrument that enables the design and test engineers to test the I3C designs for its specifications by configuring the PGY-I3C-EX-PD as controller and/or target to generate I3C traffic with margin test, error injection capabilities, conformance tests and to decode I3C protocol packets with error analysis capabilities.

I3C serial bus interface is emerging as a chosen interface for all future speed connectivity in mobile phone, automotive, CXL, DDR5 memory, SSD, PMIC applications. This could also be chosen as a low-cost, reliable interface for future embedded electronic applications to address the new data-intensive applications. DMTF uses I3C as one of the base protocols to drive the MCTP transport layer and supports application-layer protocols such as NVMe-MI, SPDM, and PLDM.

PGY-I3C-EX-PD has designed to support current and emerging applications in mobile, automotive, CXL, DDR5, SSD and PMIC applications. It supports multiple protocols on base I3C protocol such as MCTP, PLDM, SPDM and NVMe-MI. I3C Specification also supports multi lane so that user can drive more data between the controller and target.

PGY-I3C-EX-PD is upgradeable to dual and quad lane I3C Protocol Exerciser and Analysis capabilities to support future needs.

Key Protocols

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Specifications
Technical Library

PGY-I3C-EX-PD Specification

Exerciser
Configurable	1 Controller + 3 Target or 1 Secondary Controller + 2 Target
I3C/I2C Traffic Generation	Custom I3C / I2C traffic generation (Simulate real world network traffic)Custom I3C/I2C traffic generation (Simulate real world network traffic)
Transport and Application layer Protocols and script support	MCTP, NVMe-MI, SPDM, PLDM
Conformance Test Suite (CTS)	MCTP-CTS, MVMe-MI-CTS, SPDM-CTS
SCL Frequency	1Hz to 12.5MHz Note: Prodigy device supports up to 10MHz at 1V frequency as a target
Configurable Voltage Level Drive	0.9V to 3.4V Steps: 0.9-1.27V (In steps of 5mV) 1.27-1.95V (In steps of 10mV) 1.95-3.4V (In steps of 30mV)
Heat Join	Yes, supported
IBI	Yes, supported
CCC Support	All CCC are supported in Controller Side. All CCC are supported in Target except SETXTIME, ENTTM, ENTAS*
SCL Duty Cycle variation	User Defined (In Fine resolutions of 10ns)
SCL & SDA Delay	User Defined (In Fine resolutions of 18ps)
Delay between two messages	User Defined (In Fine resolutions of ns, us, ms and seconds)
Error injection	S0 to S5 types of errors specified in BBC specifications CRC errors in DDR traffic. Preamble errors in DDR traffic ACK/NACK Errors (Slave) Master Abort. Non-Standard Frames. Non-Standard Start, Stop and HDR exit patterns, slave reset Save and Load Scripts.
API Support	Support for Automation of operation using Python or C++
Protocol Analysis:
Supports	I3C & I2C protocol decode. Multilane decoding
Protocol Views	Timing Diagram View Protocol Listing View Bus-Diagram to display Protocol packets with timing diagram plot
Protocol Trigger	Auto (Trigger on any packet) Simple (Trigger on user defined I3C or I2C packet) Advanced(Multi-state & multi-level trigger with timer capability )
Capture Duration	Continuous streaming Protocol Data to host HDD/SSD
Protocol Error Report	S0 to S5 types of errors specified in the I3C specifications CRC errors in DDR traffic Preamble errors in DDR traffic ACK/NACK Errors (Target) Controller Abort Non-Standard frames Non-standard Start, Stop and HDR exit patterns.
Host Connectivity	USB 3.0/2.0 interface

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