UFS 4.0 Protocol Analyzer

Product
Overview

Datasheet

Presentation

Application
Notes

PGY-UFS4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS4.0 Protocol Analyzer. It offers protocol data capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of UFS, UniPro, and MPHY layers with the flexibility to correlate decoded data across these protocol layers. PGY-UFS4.0-PA supports PWMG1 to HSG5B data rates and two TX, and two RX lane decode. The active probe has minimum electrical loading on the device under test (DUT) and captures protocol data without affecting the performance of DUT. PGY-UFS4.0- PA Protocol Analyzer supports two-lane data. Comprehensive on the fly decoding of UniPro & UFS data enables validation of communication between UFS host and device.

PGY-UFS4.0-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPRO/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS Protocol analyzer instantaneously provides decoding of UFS, UniPro, and MPHY layers with a correlation to MPHY, UniPro, and UFS layers.

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PCIe Protocol Analyzer Datasheet

Key features

  • PCIe Gen1/2/3/4/5-X4/8 Protocol Decode and Analysis.
  • Currently supports four/eight lane PCIeGen1/2/3/4/5 Bus.
  • M2/U.2/CEM/E1.S/SD Express interposer for speeds up to PCIe Gen5 is standard offering with protocol analyzer.
  • NVME Protocol Decode Capabilities
  • Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
  • Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
  • Hardware based protocol packet (TS1, TS2 and IDLE) filter capabilities.
  • Software based search, filter-in and filter-out capabilities.
  • Hardware based protocol aware trigger capabilities based on TS1, TS2, TLP and DLLP packet contents.
  • Advanced multi-level if-then-else if trigger capabilities.
  • Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
  • Detailed view of each TLP/DLLP with all field values.
  • LTSSM Analysis for PCIe protocol traffic.
  • Memory segmentation with each segment with different trigger condition
  • Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
  • Interface to host system using USB 3.0.
  • Decoded data packets can be exported to .txt file for further analysis.
  • PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
  • Field upgradeable to enable easy maintenance and remote firmware upgrade to latest feature set.

       1. Will be supported in our future release

PCIe Gen5 Protocol Analysis with LTSSM view

PGY-PCIeGen3/4/5-PA software provides powerful protocol decode capabilities enabling engineers to quickly identify the problems in protocol layer. Software is capable of decoding the packets and provide error analysis. Different views of Protocol layer enables the user to quickly identify the problems in protocol. Powerful search, filter-in, filter-out features simplify debug activity.

PGY-PCIeGen3/4/5-PA provides sophisticated protocol trigger features which allows triggering on specific protocol event and capturing the data of interest. Auto, simple and advanced trigger features capture PCIe bus activity, specific event and monitor multiple trigger conditions and capture data around it.

Prodigy Interposers

PCIe gen 5 m.2 interposer
Prodigy M.2 Interposer (PGY-INT-M.2)
PCIe gen 5 SD express interposer
Prodigy SD Express Interposer (PGY-INT-SDX)
Prodigy CEM Interposer (PGY-INT-CEM)
PCIe gen5 U.2 Interposer
Prodigy U.2 Interposer (PGY-INT-U.2)

Key Specifications

Specifications

Data Rates Supported

PCIe Gen1, Gen2, Gen 3, Gen 4, Gen5

Link Width

Four/Eight lanes

(Four/Eight TX and Four/Eight RX).

Probes

M.2 Interposer (Standard), Optional orderable CEM, U.2, E1.S, SD Express Interposers

Solder Down Active Probes for speeds up to PCIe Gen3. (Optional)

Protocol Decode

TS1, TS2, TLP, DLLP, SDS, IDLE, EIOS, EIEOS, FTS, SKP, NVME, Decoding of Configuration register

Trace Capture Size

Supports Continuous streaming of Protocol data to Host computer SSD/HDD and Post Capture up to buffer size.

Trigger

Based on TS1, TS2, TLP, DLLP.

Connectors

Interposer Interface and Trigger in/out signal

Interface for Host Computer

USB 3.0

Host Computer Requirements

Processor: Intel i7 10th Generation or better (Equivalent)

Operating System: Windows 8.0/8.1/10/11 64bit OS.

RAM:  minimum 16GB but the product would give a faster response for 32GB/64GB/more.

Storage: 256GB SSD or more (minimum storage capacity of 1GB should be available in the hard disk drive. User can use more storage based on trace storage requirement.)

Display resolution: 1024X768.
Interface: Host computer should support USB 3.0 interface.

Dimension (WxHxD)

(W x H x D) (20.5X5X25) cms. (Tentative)

Weight

Approx. 6 kg

Power Requirement

12V, 6A DC Power Supply (AC/DC Supplied along with Analyzer).

Feel free to contact us

Do You Have Any Questions?

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Leverage agile frameworks to provide a robust synopsis for high level overviews. Iterative approaches to corporate strategy foster collaborative thinking to further the overall value proposition. Impress clients new and existing with elite construction brochures. Impress clients new and existing with elite construction.

PCIe Gen5 Protocol Analysis with LTSSM view
PCIe Gen5 Protocol Analysis with LTSSM view
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