Serial RapidIO Protocol Analyzer
The PGY-SRIO-PA is a powerful and user-friendly Serial RapidIO Protocol Analyzer that enables designers and validation engineers to efficiently analyze SRIO protocol traffic. PGY-SRIO-PA supports RapidIO Gen1 and Gen2 signaling with data rates up to 10 Gbaud per lane. It instantly decodes full RapidIO 4.1 packet formats and performs error analysis, enabling engineers to closely examine host–device interactions.
PGY-SRIO-PA is the industry best Serial Rapid IO Protocol Analyzer captures the SRIO traffic using hardware-based simple and advanced if-then-else of triggering, hardware filters and detailed protocol analysis enables efficient testing and debugging of the SRIO interfaces saving development time.
Whether in a lab or on the field, the PGY-SRIO Protocol Analyzer offers engineers a compact, field deployable, and robust solution for protocol compliance verification, debug, and system validation across a wide range of SRIO-enabled applications.
Key features
- Supports Serial RapidIO Gen1 and Gen2 protocols with real-time protocol decode.
- Operates at 1.25/ 2.5/3.125/5.0/6.25/10 per lane (user-selectable).
- Supports 1-lane and 4-lane link widths with flexible configuration via GUI
- Dual QSFP+ connectors for simultaneous Link A and Link B traffic capture
- SFP+ adapter support for single-lane testing using optical or copper modules
- Up to 64 GB deep capture buffer with configurable pre-trigger depth
- Real-time decoding of maintenance, messaging, doorbell, NWRITE, NREAD packets
- Full decode of control symbols including SOP, EOP, REPLAY, LINK requests
- Hardware-based triggering on packet fields, control symbols, or external input
- Advanced trigger logic including state-based IFTHEN-ELSE sequences
- Hardware filtering to ignore irrelevant packets during acquisition
- Powerful search and post-capture filter tools in GUI for detailed analysis
- Link-level symbol views to analyze low-level activity and IDLE patterrns
- Time-correlated dual trace view for side-by-side A→B and B→A comparison
- Export decoded results to CSV or TXT format for offline review
- Trigger-in and trigger-out ports for test system integration (LVTTL compatible)
- Easy-to-use Windows and Linux GUI for setup, capture, and analysis
- High-speed USB 3.0 interface for fast data transfer and minimal setup time
- Compact, bench-friendly hardware ideal for lab and field debug
- Field upgradeable to enable easy maintenance and remote firmware upgrade to latest feature set.
Specifications
Protocol Support | RapidIO Specification v4.1 – Class 1, Class 2 |
Baud Rates Supported | 1.25 / 2.5 / 3.125 / 5.0 / 6.25 / 10.0 Gbaud (user-selectable) |
Link Width | 1-lane (via SFP+ adapter), 4-lane (via QSFP+ port) |
Connectors | 2× QSFP+ ports (1 for Link A, 1 for Link B); Trigger In/Out – SMB (LVTTL) |
Capture Memory (Buffer) | Up to 64 GB circular buffer; 1 GB default with adjustable pre-trigger (125 |
Trigger Options | Manual, Protocol-based, External (Input), Advanced If-Then-Else State |
Filter Capabilities | Hardware filter for packets and control symbols; software-based |
Raw Data Mode | Symbol-level (after 8b/10b decoding), full field decode available |
Host Interface | USB 3.0 Gen 1, USB Type-C |
Supported OS | Windows 10/11 (64-bit), Linux Ubuntu 22.04 LTS |
Power Supply | 12V DC, 6A (adapter included) |
Dimensions (W × H × D) | Approx. 20.5 × 5 × 25 cm (same enclosure as PCIe analyzer) |
Weight | Approx. 6 kg |
Status Indicators | Link status LEDs per lane, Trigger and Activity indicators |
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