UFS 4.0 Protocol Analyzer





PGY-UFS4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS4.0 Protocol Analyzer. It offers protocol data capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of UFS, UniPro, and MPHY layers with the flexibility to correlate decoded data across these protocol layers. PGY-UFS4.0-PA supports PWMG1 to HSG5B data rates and two TX, and two RX lane decode. The active probe has minimum electrical loading on the device under test (DUT) and captures protocol data without affecting the performance of DUT. PGY-UFS4.0- PA Protocol Analyzer supports two-lane data. Comprehensive on the fly decoding of UniPro & UFS data enables validation of communication between UFS host and device.

PGY-UFS4.0-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPRO/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS Protocol analyzer instantaneously provides decoding of UFS, UniPro, and MPHY layers with a correlation to MPHY, UniPro, and UFS layers.

UART Protocol Exerciser and Analyzer Datasheet

Key features

  • Supports custom UART traffic generation
  • Simultaneously generate UART traffic and Protocol decode of the bus
  • Variable UART baud rates
  • Continuous streaming of protocol data to the host computer to provide a large buffer
  • A timing diagram of Protocol decoded bus
  • Listing view of Protocol activity
  • Error Analysis in Protocol Decode
  • Ability to write exerciser script to combine multiple data frame generation at different data speeds
  • USB 2.0/3.0 host computer interface
  • API support for automation in Python or C++

Multi-Domain view

Multi-domain View provides the complete view of UART Protocol activity in a single GUI. Users can easily set up the analyzer to generate UART traffic using a GUI or script. Users can capture Protocol activity at a specific event and decode the transition on the UART line. The decoded results can be viewed in the timing diagram and Protocol listing window with auto–correlation. This comprehensive view of information makes it the industry’s best, offering an easy-to-use solution to debug the UART protocol activity.


PGY–UART–EX–PD supports UART traffic generation using GUI and Script. Users can generate simple traffic generation using the GUI to test the DUT. Script-based GUI provides flexibility to emulate the complete expected traffic in the real world including error injections. In this sample script user can generate UART traffic as below:

Timing Diagram and Protocol Listing View

The timing view provides the plot of TX signals with a bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in the timing diagram for any timing errors.
The protocol window provides the decoded packet information in each state and all packet details with error info in the packet. The selected frame in the Protocol listing window will be autocorrelated in the timing view to view the timing information of the packet.

Setup View

Users can configure the PGY-UART-EX-PD for different baud rates, for different configurations of Data width and Stop bits. Users can also choose whether the parity is odd or even depending on the data type being used and also select the data shift type.

Key Specifications

UART Specifications

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