UFS 5.0
Protocol Analyzer
PGY-UFS5.0-EX-PA UFS5 Protocol Exerciser and Analyzer is an industry leading product and tested on a real-world UFS5.0 device under test (DUT) at HSG6B datarate. UFS2.X/3.X/4.X are widely used in many different applications such as mobile, automotive, gaming, and consumer products. UFS5.0 with very high datarate of 46.64Gbps per lane would target data intensive applications in mobile, automotive, gaming and consumer products. PGY-UFS5.0-EX-PA supports UFS2.X to UFS5.0 datarate along with PWM and High Speed link up to address the wide range user requirements.
Industry first PGY-UFS5.0-EX-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication from PWMG1 to HSG6B data rate (46.64Gbps per lane data rate with PAM4 signaling). Active probe with least loading provides the flexibility to tune the probe to meet signal conditioning needs of the different device under test to ensure reliable operation of the test setup to capture UFS protocol data. MPHY/UniPro/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS5.0-EX-PA Protocol analyzer instantaneously provides decoding of UFS, UniPro and MPHY layers with a correlation to MPHY, UniPro and UFS layers.
PGY-UFS5.0-EX-PA supports optional UFS5 host and device emulation capabilities making industry first solution to support UFS5 host and device testing capabilities. UFS device emulation supports HSG6 rate A and HSG6 rate B traffic generation with response to HS Linkup, read and write operations in a software-controlled environment with FPGA PHY
support (No MPHY Support). UFS host emulation supports UFS and UniPro conformance test suite along with custom test cases to generate to protocol traffic generation for testing the UFS5 devices.
Key Features
- Full UFS 5.0 protocol analysis with backward compatibility to UFS 2.x, 3.x, and 4.x
- Supports MPHY 3.0, 4.0, 4.1, 5.0, and 6.0, UniPro 1.6, 1.8, 2.0, and 3.0, and PACP layers
- Data rates from PWM G1 to HSG6 Rate A and B, including PAM4 operation up to 46.64 Gbps per lane
- One-lane and two-lane configurations supported (2 TX and 2 RX)
- Industry-first UFS 5.0 protocol analyzer validated on real UFS 5.0 DUTs at HSG6B data rates
- Deep protocol decode at MPHY, UniPro, PACP, and UFS layers with time-correlated views for faster debug
- Protocol-aware triggering on MPHY, UniPro, PACP, and UFS packet content
- Trigger IN and Trigger OUT support to synchronize with external instruments such as oscilloscopes
- Continuous protocol data streaming to host system with 16 GB internal acquisition memory, upgradeable to 32 GB
- Multiple buffer modes including live capture, post-acquisition analysis, and circular buffer operation
- Advanced protocol validation and error detection, including CRC error count, sequence number mismatch, PACP request-confirm mismatch, and command-response mismatch
- Power-aware analysis with PACP packet separation for detailed power mode transition debug
- Flexible probing solutions including solder-down active probes, power divider interposers, board-to-board interposers, and mSMP connector-based probes
- Active probe architecture with minimal loading, ensuring reliable capture at high data rates
- Comprehensive analytics views for UniPro and UFS layers with powerful search, filter-in, and filter-out capabilities
- Decoded protocol data export in CSV format for offline analysis and reporting
- USB 3.0 Type-C host interface for high-speed data transfer and control
- Upgradeable architecture supporting optional UFS 5.0 host and device emulation capabilities
- Self-certified CE and RoHS compliant, suitable for lab and field deployment
Test Setup
PGY-UFS5.0-EX-PA UFS5 Protocol Analyzer probes the MPHY interface between the host and device using the Board-to-Board interposer. The MPHY signals are actively split in the Board-to-Board interposer and output is connected to host or device inputs and other output to the UFS5 Protocol Analyzer. The miniSMP connectors in Board to Board interposer enables easy connection between the interposer and UFS5 Analyzer input. The Board-to-Board interposer powered and digitally controlled from the PGY-UFS5.0-EX-PA Protocol hardware unit.
PGY-UFS5.0-EX-PA software which runs in windows OS interfaces to the PGY-UFS5.0-EX-PA hardware unit using USB3.0 interface. The software enables configuration of protocol analyzer and setting up the Board-to-Board interposer for reliable data capture. The Protocol Activity captured by the PGY-UFS5.0-EX-PA hardware unit is decoded and display the Protocol data in MPHY layer, PACP, UniPro and UFS including TFS packet information.
Windows based protocol analysis software provides industry best protocol correlation between UFS to UniPro and MPHY layers. Time correlation between the different protocol layers significantly reduces debug time of designs. Floating window design of this software allows engineers to view UFS view, UniPro view and MPHY view on different computer monitors and automatically correlate the UFS packets to MPHY layer. This makes analysis of protocol data very easy while analyzing the gigabytes of protocol information.
PGY-UFS5.0-EX-PA Software
PGY-UFS5.0-EX-PA Software can display each UFS packet parameters in a listing window. Right click lists all the packet parameter for user selection. User can color code the fonts or background color for easy identification for each UFS packet.
PGY-UFS5.0-EX-PA Software separates the PACP packets in a separate view for easy analysis of power mode change packets and link to UniPro packets. Users can view the MPHY states stall, prepare, sync information in UniPro view apart from user selection for DL_Data and AFC/NACK Packet details.
PGY-UFS5.0-EX-PA Software has powerfull protocol validation, search and filter capacities. While decoding the acquired, software automatically reports errors and volulation in protocol events. User can search these events at a click of button. Software provides flexibility define the search or filter conditions at protocol packet level or by spectific attributes within the packet.
PGY-UFS5.0-EX-PA Software Provides detailed analysis of response from UFS device to the command and its operation. This enables very easy validation of UFS protocol for correctness and provides insight to the UFS state machine performance.
PGY-UFS5.0-EX-PA Protocol Analyzer Specification
Specification | Features |
Data Rates Supported | PWM G1 , High Speed Gear 1, Gear 2, Gear 3, Gear 4, Gear 5 and Gear 6 Rate A and B |
Link width | Configurable for 1TX/1RX or 2TX/2RX |
Lanes supported | Two data lanes (2 TX and 2 RX) |
Probes | older Down Active Probes for data rate upto HSG5B |
Protocol Decode | UFS, UniPro, PACP, MPHY , fillers, Hibernate entry and exit, line reset |
Protocol supported | UFS v2.X/3.X/4.X/5.0 |
Signal swing | 350mV for NRZ and 500mV and above for PAM4 (500mV) |
Trace Capture Size | Supports Continuous streaming of Protocol data to Host computer SSD/HDD. Internal acquisition memory of 16GB expandable up to 32GB |
Trigger | Auto, PACP, UniPro, UFS protocol packet content, advanced if-then-elseif triggers |
Storage Modes | Continuous capture, circular buffer |
Protocol Analysis | Protocol Trace analysis, CRC error checks, Monitor UFS tag and UniPro sequence number for any missing packets |
Tester Port | Supported to UFS host and device emulation interface. |
Front Panel Connectors | Interface for Active probes. Exclusive Trigger In and OUT connectors |
Interface for Host Computer | USB3.0 for Protocol analysis and update the FPGA firmware |
Host Computer Requirements | Processor: Intel i7 or AMD Ryzen 7 or greater |
Temperature | °C to +50 °C (32 °F to 122 °F) |
Dimension | 395.00 X 241.50 X 83.70 MM |
Weight | Approx. 5.0Kg |
Power Requirement | 12V, 5A DC Power Supply (AC/DC Supplied along with Analyzer) |
ESD | Regulatory CE marked and RoHS self compliant |
UFS4/5 Probing Solutions
Probing UFS signal is one of the key challenges in reliable UFS protocol decode. In most of the DUT, test points are located close to each other without enough space to solder the probe tips. Prodigy developed miniaturised Solder-in probe tips that can be soldered directly to test pads between the UFS host and device. This probe tip has high analog bandwidth to boost the HSG5B (23.32Gbps) signals. Active circuit in probe tip efficiently drives the low power MPHY signal to UFS4.0 Protocol Analyzer for error free Protocol Analysis at UFS4.0 speeds.
Many of the UFS4.0 development platforms have SMPM connector to access the MPHY Signals. To probe such device, Prodigy Technovations offers SMPM probe tips. SMPM probe tips has mating SMPM connector with DUT. This makes it convenient connect to the DUT and analyze UFS4.0 Protocol data. SMPM coaxial cables are required to connect the power divider to UFS test setup. These cables are to be separately arranged by user.
For UFS 5 Probing, Prodigy Technovation Board to Board interposer and mSPM power divider interposer. Prodigy Technovations can develop a custom probing solution based on the customer device under test and also provide the necessary technical support.
UFS 5 Host Emulation Tester
(Under Development)
PGY-UFS5.0-EX-PA is an UFS5 Protocol Analyzer that can be upgraded to UFS4/5 Protocol Exerciser (Tester) with additional external UFS4.0/5.0 tester board. Host emulator enables the testing of UFS devices for Unipro and UFS conformance tests as well custom test cases. Users can run UFS4/5 CTS, UniPro2.0/3.0 CTS and write custom test scripts to develop their custom test cases to test the UFS4/5 device.
PGY-UFS5.0-EX-PA with UFS5 Exerciser capabilities forms the industryʼs best solution to test the UFS5 systems and UFS5 devices by detailed protocol analysis as well as powerful tester capabilities resulting reliable UFS4/5 products and faster time to market.
UFS 4/5 Host Exerciser:
Prodigy Technovations has developed UFS5.0 Tester board which can be externally interfaced to PGY-UFS5.0-EX-PA and upgrade the PGY-UFS5.0-EX-PA to support UFS4/5 protocol Test needs. The TX0 and TX1 lanes from PGY-UFS5.0-EX-PA drive the PACP, UniPro and UFS5 protocol packets at different data rate to the UFS4/5 device that is placed in UFS5 tester board. UFS5 tester board is powered by a power supply from PGY-UFS5.0-EX-PA. Execrciser port in PGY-UFS5.0-EX-PA drives the protocol traffic as well as receives the response from DUT for protocol analysis. The software in PGY-UFS5.0-EX-PA provides the flexibility write custom test cases as well as run automated UFS and Unipro conformance test suite.
UFS4/5 Conformance Test Suite (CTS)
PGY-UFS5.0-EX-PA automatically runs UFS CTS test cases and analysis the test cases and analysis the test result and provide pass/fail test results. Following test cases are supported in PG-UFS5-EX-PA following test cases. UFS CTS covers both SCSI and Protocol tests covering all functionalities of the UFS Protocol. These 200 plus test cases can be run in a click of button different rate and test reports can be generated for records.
PGY-UFS5.0-EX-PA automatically runs UFS CTS test cases and analysis the test cases and analysis the test result and provide pass/fail test results. Following test cases are supported in PG-UFS5-EX-PA following test cases. UFS CTS covers both SCSI and Protocol tests covering all functionalities of the UFS Protocol. These 200 plus test cases can be run in a click of button different rate and test reports can be generated for records.
Sl.No. | UFS SCSI Tests | Total |
1 | Inquiy | 5 |
2 | Request Sense | 4 |
3 | Mode Sense | 19 |
4 | Mode Select 10 | 17 |
5 | Unmap | 6 |
6 | Start Stop Unit | 8 |
7 | Read Capacity | 1 |
8 | Format Unit | 3 |
9 | Test Unit Ready | 2 |
10 | Write 6 | 3 |
11 | Write 10 | 6 |
12 | Read 6 | 3 |
13 | Read 10 | 6 |
14 | Verify 10 | 4 |
15 | Send Diagnostic | 3 |
16 | Report Luns | 9 |
17 | Synchronize Cache | 5 |
18 | Pre fetch 10 | 5 |
Total | 109 |
Sl.No. | UFS Protocol Tests | Total |
1 | Context Management | 3 |
2 | Task Management | 6 |
3 | Boot | 2 |
4 | Read Descriptor | 12 |
5 | Write Descriptor | 3 |
6 | Set Flag | 9 |
7 | Read Flag | 8 |
8 | Clear Flag | 4 |
9 | Toggle Flag | 4 |
10 | Read Attribute | 17 |
11 | Write Attribute | 25 |
12 | Power Mode | 6 |
13 | UPIU | 2 |
14 | UPIU Flags | 3 |
15 | Unit Attention | 15 |
Total | 119 |
UniPro 2.0 Conformance Test Suite
PGY-UFS5.0-EX-PA automatically runs Unipro 2.0 CTS test cases and Analysis the test cases and analysis the test result and provide pass/fail test results. Following test cases are supported in PGY-UFS5.0-EX-PA following test cases.
UniPro2.0 Conformance Test Suite supports UnIPro 2.0 CTS as per MIPI Alliance Specification. User can select all PHY Adapter Layer tests, Data Link Layer Related Tests, Network Layer Related Tests, Transport layer related tests and SME related tests. Based on user selection will be run and results are displayed with pass/fail criteria. User can analyzer test results for failure condition of by reviewing the protocol decoded data. User can use the drop menu to select the specific test case and run it and view the results.
Custom Test Case Development
PGY-UFS4-PA with UFS4 tester board and the software provides industry best custom UniPro and UFS Test case development platform for UFS3.1/4.0 devices.
User can set the prepare time, sync length, burst speed, fast or fast auto mode, one lane or two-lane configuration. User can easily define each of the attributes of the UniPro or UFS packets.
All these test cases can be saved and recalled for future use.
Test report of UniPro CTS, UFS 4.0 CTS and Custom test cases can be generated in mht format.
PGY-UFS5.0-EX-PA Software which provides additional views to write the UFS test cases, as well as ready to use UFS CTS and UniPro 2.0/3.0 CTS. User can write easily use Prodigy developed scripting language which self-guiding the user to write the script at ease. By selecting the UFS CTS and UniPro CTS in ‘viewʼ menu of PGY-UFS5.0-EX-PA software user can easily access the Conformance Test Suite and run it press of a single button.
PGY-UFS5.0-EX-PA Device Emulator
(Under development)
PGY-UFS5.0-EX-PA automatically runs Unipro 2.0 CTS test cases and Analysis the test cases and analysis the test result and provide pass/fail test results. Following test cases are supported in PGY-UFS5.0-EX-PA following test cases.
PGY-UFS5.0-EX-PA optionally configured as a UFS5 device emulator to enable the testing of UFS5 host testing purpose. User can to do the single stepping of Protocol command and UFS5 device emulator provides expected response to the command. The response is preprogrammed through the host computer. This provides the flexibility to change UFS5 prepare, sync, filler for any given packet. PGY-UFS5.0-PA supports FPGA Transceivers as a Physical layer.
Typical protocol flow can be as below specifications
UFS 4/5 Host Under development can send specific traffic to PGY-UFS5.0-EX-PA. It will respond with Preprogrammed response to the Host protocol Packet. Design and test engineers can analysis the host response to device Emulator.
UFS 5 Device Emulator Specification:
Specification | Device Emulation Support |
PHY Layer | FPGA Transceiver PHY for NRZ and PAM4 |
Signal Amplitude | 500mv to 600mV amplitude |
Common Mode Voltage | TBD |
Data rate | PWM1 to HSG6 Rate A and B |
Link up Sequence | HS Linkup and Low speed PWM linkup |
Number of lanes | one lane or two lane |
MPHY Burst support | Fast Mode |
Prepare Time | Variable (Fine details TBD) |
NRZ Sync | Variable (TBD) |
PAM4 Sync | Variable (Yes) |
Align pattern | Supported (correct and erroneous error) |
RS-FEC | Supported |
Scrambler | Supported |
Fillers | Variable (Detailed TBD) |
Error Injections in data | Correctable and non correctable errors |
UniPro layer support | DL_Data and AFC support |
UFS Layer response | Yes, managed from software layer |
Weight | Approx. 5.0Kg |
Power Requirement | 12V, 5A DC Power Supply (AC/DC Supplied along with Analyzer) |
ESD | Regulatory CE marked and RoHS self compliant |
Response to following commands is configurable from Host computer of UFS5 Device Tester
UFS Layer | Commands and UIC |
UFS Commands | FORMAT UNIT, READ (6) and READ (10), READ CAPACITY (10), REQUEST SENSE, SEND DIAGNOSTIC,UNMAP, WRITE (10), INQUIRY, REPORT LUNS, READ BUFFER, TEST UNIT READY, WRITE BUFFER, SECURITY PROTOCOL IN and SECURITY PROTOCOL OUT, MODE SELECT (10) and MODE SENSE (10), PRE-FETCH (10), START STOP UNIT, SYNCHRONIZE CACHE (10), VERIFY (10), READ (16), WRITE(16), PRE-FETCH (16), |
Query Request Commands | C) UFS Interconnect (UIC) Commands to get and set M-PHY and UniPro Attributes |
UIC Commands | UFS Interconnect (UIC) Commands to get and set M-PHY and UniPro Attributes. |
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