During the power-on sequence of a PCI Express (PCIe) system, the reference clock (REFCLK) and sideband signals may not have reached their required stability or operating tolerance. The PERST# (PCIe Reset) signal is an active-low, open-drain output driven by the Root Complex (RC). It is used to hold the endpoint (EP) devices in reset while the system’s power and clock signals stabilize. The PERST# signal remains asserted (held low) until the RC confirms that the power rails and REFCLK are stable. Once these are within specification, the RC deasserts (releases) PERST#, signaling to endpoint devices that the system is ready to begin PCIe link initialization.
From the endpoint’s perspective, the deassertion of PERST# acts as a global reset release and indicates that power and clocks are valid, allowing the endpoint to start its PCIe link training and initialization process.
To ensure successful link initialization and operation between the Root Complex (RC) and Endpoints (EPs), the following timing requirements must be observed:
Symbol | Parameter | Min | Max | Units | Note |
TPVPGL | Power Valid to PERST# input inactive | Note 1 | ms | 2 | |
TPERST#-CLK | REFCLK stable before PERST# de-assertion | 100 | µs | ||
TFAIL | Power level invalid to PERST# assertion | 500 | ns | ||
TPERST | Assertion time of PERST# | 100 | |||
TPERSTSLEW | Slew rate of PERST# transition to de-asserted | 50 | mV/ns | 3 |
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