Multi I3C bus decoding for Serial Presence Detect (SPD) in DDR5

Serial Presence Detect (SPD) is a standardized method to automatically access the information about DDR3/4/5 memory modules. When a electronic system us powered on, it starts doing automatically configuring the system by identifying different hardware components. SPD is a feature in DDR3/4/5 enables the electronic system to know the DDR memory details and its timing information. DDR3/4 memory modules use SM Bus to provide this information. In case latest very high speed memory DDR5 uses low voltage signals (1V)  I3C interface to read the memory details and its timing information.

Fig 1. Typical I3C Bus architecture in DDR5 based system design

 

Typical I3C bus architecture is shown in Fig.1. When host controller is interfaced DDR5 modules using SPD5 hub. During the design and testing stage, it can be very challenging to monitor all the I3C bus in this architecture using off the shelf oscilloscopes.

Some of the key requirements to debug these designs as below

1. Need logic analyser which can work with 1V signal amplitude.
2. It should be possible to acquire different I3C logic activities at the same time.
3. It should also possible decode all these I3C buses may be operating at different rate varying from 100KHz to 12.5MHz
4. Monitor specific event in the I3C bus.

 

Prodigy Technovations has developed industry first multi-channel I3C decode solution on the existing logic analyser. It has following capabilities.

1. Identifies logic levels at 1V signal amplitude.
2. Decode eight I3C buses at the same time with time synchronization of all the I3C buses.
3. Bus diagram for all the I3C buses
4. Power full trigger capabilities
5. Asynchronous sampling1GS/sec enables capturing varying clock rate I3C protocol events

PGY-LA-Multi-I3C is a 16 Channel logic analyser. Which has the following key capabilities

• 1GS/Sec asynchronous sampling capabilities
• Eight I3C Bus decoding capabilities
• Trigger on I3C Protocol Packet content

Multichannel I3C Protocol decode analysis result view as shown in fig3.

Fig. 2. Listing of Multi I3C channel decode and digital timing diagram

 

Listing window list decodes the i3C packets from different I3C bus and displays it. Timestamp is used to list packet in the order so that user can the events happening with respect to the time.

Software also displays the timing waveform with bus diagram. Bus diagram will have each I3C packet information for easy debug purposes.

To capture the traffic at specific event, user can set the trigger condition based on I3C Protocol packet content.

Change Trigger condition for some other CCC or private

Fig. 3 I3C protocol Aware Trigger GUI

 

User can export this data to file in CSV format. This DATA can be viewed Excel software for further analysis

       Fig4. CSV export in Excel software

 

Exported data will time stamp, I3C bus name, protocol packet content and frequency of operation.

PGY-LA-Multi-I3C provides most comprehensive solution address the DDR5 system requirements for  serial peripheral detect bus. It can decode all eight channels with listing and timing diagram view.  Abilities to export this data makes it most convenient to use it.

 

Prodigy Technovations provides most comprehensive solution to develop I3C Technology. Following are our products.

PGY-I3C-EX-PD   I3C Protocol Exerciser and Analyzer with optional CTS: https://prodigytechno.com/device/i3c-protocol-analyzer/

PGY-I3C-EX-PD Lite I3C Protocol Exerciser and Analyzer with fixed voltage

PGY-I3C-USB-ADT I3C to USB adapter

 

Learn more about our comprehensive I3C solutions: https://prodigytechno.com/i3c-protocol-solutions/