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Lead FPGA Engineer

Chandrala Brijesh

Chandrala Brijesh is a Lead FPGA Engineer with experience in Architecture, multi Clock Domain designs, and High-speed Protocols. He has deep expertise in high-speed memory protocols like UFS as well as the latest protocols like MIPI I3C. Brijesh is a B.E.graduate of VTU University and has done Post Graduation in VLSI and Embedded System from Pune University.

Professional Skills

Planning 80%
Consulting 95%
Management 89%
Development 90%

Experience & Activities

Chandrala Brijesh is a Lead FPGA Engineer with experience in  Architecture, multi Clock Domain designs, and High-speed Protocols. He has deep expertise in high-speed memory protocols like UFS as well as the latest protocols like MIPI I3C. Brijesh is a B.E.graduate of VTU University and has done Post Graduation in VLSI and Embedded System from Pune University.