Protocol Exercisers & Analyzers

I3C Protocol Exerciser and Analyzer – Lite

Model No: PGY-I3C-Lite

The PGY-I3C Lite is a Protocol Analyzer with multiple features to capture and debug communication between host and design under test. I3C Serial bus interface is emerging as a chosen interface for all future sensor connectivity in mobile phone and automotive industries. This could also be chosen as a low-cost, reliable interface for future embedded electronic applications to address the new data- intensive applications. The I3C-Lite enables design and test engineers to test their I3C designs as per specifications by configuring the I3C-Lite as Master/Slave to generate I3C traffic and decode I3C protocol packets.

Key Protocols
  • I3C
  • Free Online Technical SupportFree Online Technical Support
  • Free Software UpdatesFree Software Updates
  • Global Sales SupportGlobal Sales Support
  • Evaluation Units AvailableEvaluation Units Available
  • Key Features
  • Specifications
  • FAQs

Users can also set triggers on specific I3C Protocol packets to capture an event of interest. The PGY-I3C Lite unit comes in a portable form factor that makes it an efficient and easy-to-carry tool. Flexible report generation capabilities in PDF and CSV formats with the ability to attach images allow engineers to save the captured protocol information for future analysis. Saved traces can be loaded into the software that allows users to analyze the captured traffic for offline analysis.

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Features/SpecificationsDescription
Exerciser:
Configurable1 Master + 1 Slave*
I3C/I2C Traffic GenerationCustom I3C/I2C Traffic Generation
SCL Frequency Variation100KHz-12.5MHz*
Simulate Real-world trafficNot supported (Only 4 lines of scripts can be sent at a time using GUI) *
Voltage Levels supportedFixed 1V, 1.2V, 1.8V, 2.5V, and 3.3V*
Hot-Join and IBISupported
IBI Response FeatureNot supported*
Clock to Data Delay (tCO)Supported, in steps of 10ns*
Delay Between Messages (tIMG)Supported, in steps of ns, us, ms and seconds
Set up and Hold VariationsNot Supported*
Error injectionNot Supported*
CTS v1.1 SupportNot Supported*
API SupportSupported in Python using Opt API*
CCC SupportAll CCC's are supported on the Master side as per I3C v1.0*
Protocol Analyzer:
Protocol AnalysisI3C/I2C
Analyzer Resolution4ns
Protocol ViewsTiming Diagram View
Protocol Listing View
Bus-Diagram View
Protocol TriggerAuto Trigger & Message Trigger
Advanced TriggerNot Supported*
Capture DurationContinuous streaming of protocol data to host HDD/SSD for long-duration capture
Protocol Error ReportS0 to S5 types of errors as specified in the I3C specifications
CRC errors in DDR traffic
Preamble errors in DDR traffic
ACK /NACK Errors (Slave)
Master Abort
Non-Standard frames
Non-standard Frames
Start, Stop and HDR exit patterns.
Custom CommandsNot Supported*
Host ConnectivityUSB 2.0/3.0

* Indicates that the I3C-Main unit supports this feature or has additional features compared to what is offered on the Lite unit.

An I3C analyzer helps engineers validate MIPI I3C implementations by providing visibility into real-time bus activity and device interactions. It can be used to verify Controller and Target behavior, I3C protocol compliance, dynamic addressing, Common Command Codes (CCCs), and other I3C operations during development and system validation.

An I3C analyzer can capture and analyze bus transactions to help engineers identify protocol errors, unexpected device responses, transaction issues, and communication problems during I3C device testing.

An I3C analyzer captures and analyzes existing bus traffic, while an I3C exerciser generates controlled traffic to test device behavior. Combining both functions allows engineers to generate, capture, and analyze I3C transactions during validation.

I3C protocol traffic is debugged by capturing transactions, analyzing communication sequences, and checking Controller and Target responses. Protocol debugging helps engineers locate incorrect transactions, unexpected responses, and other communication issues.

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