UFS 5.0 Protocol Exerciser and Analyzer

The PGY-UFS5.0-PA supports automatic tuning of CTLE (Continuous-Time Linear Equalizer) parameters for both solder-down
and board-to-board interposers, enabling reliable capture of UFS5.0 protocol traffic.
The UFS5.0 Protocol Analyzer interfaces with the probe module’s redriver IC through an SPI interface to control and optimize the
CTLE settings. Initially, the analyzer applies a default CTLE configuration that is suitable for a wide range of UFS4.x devices under
test and continuously monitors the eye diagram within the PGY-UFS5.0 Software.
The software measures key signal integrity parameters, including eye height and eye width. If the detected eye opening is
insufficient for reliable data capture, the analyzer automatically adjusts the CTLE parameters in the redriver IC to optimize signal
quality and improve the eye opening.
This automatic CTLE tuning mechanism ensures robust signal integrity and enables accurate, error-free capture of UFS5.0
protocol data across different DUT configurations.

Intelligent Signal Optimization

• Automatically tunes CTLE parameters in solder‑down and board‑to‑board interposers, ensuring flawless UFS5.0 protocol
  data capture.
• Built‑in intelligence controls the redriver IC via SPI, eliminating manual adjustments and reducing setup complexity.

Eye Diagram Monitoring

• Leverages the PGY‑UFS5.0 Software to continuously monitor eye height and width.
• Detects insufficient eye openings and instantly adjusts CTLE parameters to guarantee clear, reliable signal integrity.

Benefits

• Zero Guesswork: Autotuning ensures optimal CTLE settings without manual intervention.
• Accuracy Assured: Maintains a wide, stable eye opening for error‑free data capture.
• Future‑Ready: Compatible with widely used UFS4.0 devices while also optimized for UFS5.0 validation.
• Efficiency Boost: Engineers save valuable debug time with automated signal conditioning.

PGY-UFS5.0-EX-PA Software can display each UFS packet parameters in a listing window. Right click lists all the packet
parameter for user selection. User can color code the fonts or background color for easy identification for each UFS packet.
PGY-UFS5.0-EX-PA Software separates the PACP packets in a separate view for easy analysis of power mode change packets
and link to UniPro packets. Users can view the MPHY states stall, prepare, sync information in UniPro view apart from user
selection for DL_Data and AFC/NACK packet details.

PGY-UFS5.0-EX-PA Software has powerfull protocol validation, search and filter capacities. While decoding the acquired,
software automatically reports errors and volulation in protocol events. User can search these events at a click of button.Software
provides flexibility define the search or filter conditions at protocol packet level or by spectific attributes within the packet.

PGY-UFS5.0-EX-PA Software Provides detailed analysis of response from UFS5.0 device to the command and its operation. This
enables very easy validation of UFS5.0 protocol for correctness and provides insight to the UFS5.0 state machine performance.

The PGY5000 Solder-Down Probe combines precision engineering with ease of handling, giving you dependable access to critical signals in dense layout, a perfect solution for advanced UFS5.0 validation and debug. PGY Solder-Down Probe is Flexible, Feather-Weight Probing Solution. The Compact Probe Design features a probe module with flying probe wires. Each flying wire terminates in a miniature probe-tip PCB with an isolation resistor at one end and an ARF connector at the other. Flexible and feather-weight construction makes it simple to handle. Close-pitch design allows convenient soldering of the probe tip to the last accessible point using a very small jumper wire. Provides engineers with a stable, low-intrusion connection for high-speed signal access. PGY-5000 maintains signal integrity for accurate protocol analysis. Typical Slicer and SNR plots to demonstrate performance and reliability. The PGY5000 Solder-Down Probe combines precision engineering with ease of handling, giving you dependable access to critical signals in dense layout, a perfect solution for advanced UFS5.0 validation and debug. PGY Solder-Down Probe is Flexible, Feather-Weight Probing Solution. The Compact Probe Design features a probe module with flying probe wires. Each flying wire terminates in a miniature probe-tip PCB with an isolation resistor at one end and an ARF connector at the other. Flexible and feather-weight construction makes it simple to handle. Close-pitch design allows convenient soldering of the probe tip to the last accessible point using a very small jumper wire. Provides engineers with a stable, low-intrusion connection for high-speed signal access. PGY-5000 maintains signal integrity for accurate protocol analysis. Typical Slicer and SNR plots to demonstrate performance and reliability.

The probe module integrates an amplifying circuit that compensates for signal loss. This ensures clean, reliable decoding of UFS5.0 signals at 46.6 Gbps PAM4 data rate when used with the PGY-UFS5.0-EX-PA Protocol Analyzer. Signal quality depends on soldering precision of the probe tip and Parasitic effects on the DUT (Device Under Test). Proper handling of soldering and parasitic on the DUT ensures optimal eye opening and error-free analysis.

PGY-5001 UFS5.0 SMPM probe is designed for UFS5.0 devices under test where MPHY6.0 UFS5.0 signals are accessible via an SMPM connector. The PGY5001 probe connects directly to the DUTʼs SMPM interface, ensuring a stable and secure connection. This provides a robust probing solution that minimizes noise and distortion. PGY-5001 compensates for signal loss and amplifies signals, maintaining integrity at highspeed UFS5.0 data rates. Also ensures errorfree UFS5.0 protocol analysis by delivering clean, amplified signals to the analyzer. Test engineers to validate nextgeneration UFS designs with confidence and precision.

In UFS5.0 product development, host and device are typically interconnected using SMPM cables, leaving no direct access to signals on the validation platform. The PGY-INT-ACT-PD solves this by actively splitting signals between host and device, enabling engineers to capture and analyze protocol activity without disrupting connectivity. PGY-INT-ACT-PD Maintains signal integrity at 46.6 Gbps PAM4 data rates. Compensates for signal loss to ensure error-free UFS5.0 protocol analysis. Ensures Guarantees reliable operation for PGY-UFS5-EX-PA Protocol Analyzer, empowering accurate validation. Industry-Best Active Divider Technology Provides real-time access to M-PHY6.0/UFS5.0 signals. Designed for engineers who demand precision, reliability, and speed in next-generation UFS5.0 validation.

The PGY5002 UFS5.0 BoardtoBoard Interposer provides seamless access to UFS5.0/MPHY6.0 signals. It is designed for devices under test (DUTs) where direct access to these signals is not available. By exposing critical UFS5.0 and MPHY6.0 interfaces, it enables stable and accurate protocol analysis during validation and debug.
PGY-5003 consists of bottom PCB, Connector and a top PCBA. A bottom PCB is positioned in place of the UFS5.0 device BGA area. A highspeed connector is mounted on the bottom PCB, enabling direct interface. A top PCBA is attached to this connector, housing the UFS5.0 device socket. The top PCBA provides access to MPHY 6.0/UFS5.0 signals. Signals can be tapped actively or passively, ensuring flexibility in analysis. This setup enables engineers to capture and decode UFS5.0 protocol traffic even when DUTs do not expose these signals directly. PGY-5002-B2B-CNT form the industry best probing solution with very good slicer eye opened and SNR of greater than 24dB*.

To Support UFS5.0 Host Validation, P5003 Host Validation Board is the most suitable solution. In the UFS5.0 host controller validation board, UFS5.0 signals can be terminated at SMPM connector and low speed signals such as clock, reset, high link up signals to a GPIO connector. PGY-5003 UFS5.0 Host Validation Board can be interfaced with SMPM connectors on UFS5.0 host controller board. Integrated probes on UFS5.0 Host Validation Board enables easy access to UFS5.0/MPHY6.0 signals for protocol analysis and maintains required SI. Test Engineers can easily test different vendor UFS5.0 devices by replacing the UFS5.0 devices using the high performance UFS5.0 socket on the UFS5.0 host validation board and protocol analysis for any protocol failure.

PGY-UFS5.0-EX-PA is an UFS5.0 Protocol Analyzer that can be upgraded to UFS4/5 Protocol Exerciser (Tester) with additional external UFS4.0/5.0 tester board. Host emulator enables the testing of UFS5.0 devices for Unipro and UFS5.0 conformance tests as well custom test cases. Users can run UFS4/5 CTS, UniPro2.0/3.0 CTS and write custom test scripts to develop their custom test cases to test the UFS4/5 device. PGY-UFS5.0-EX-PA with UFS5.0 Exerciser capabilities forms the industry’s best solution to test the UFS5.0 systems and UFS5.0 devices by detailed protocol analysis as well as powerful tester capabilities resulting reliable UFS4/5 products and faster time to market.

Prodigy Technovations has developed UFS5.0 Tester board which can be externally interfaced to PGY-UFS5.0-EX-PA and upgrade the PGY-UFS5.0-EX-PA to support UFS4/5 protocol Test needs. The TX0 and TX1 lanes from PGY-UFS5.0-EX-PA drive the PACP, UniPro and UFS5.0 protocol packets at different data rate to the UFS4/5 device that is placed in UFS5.0 tester board. UFS5.0 tester board is powered by a power supply from PGY-UFS5.0-EX-PA. Execrciser port in PGY-UFS5.0-EX-PA drives the protocol traffic as well as receives the response from DUT for protocol analysis. The software in PGY-UFS5.0-EX-PA provides the flexibility write custom test cases as well as run automated UFS5.0 and Unipro conformance test suite.

PGY-UFS5.0-EX-PA automatically runs UFS5.0 CTS test cases and analysis the test cases and analysis the test result and provide pass/fail test results. Following test cases are supported in PGY-UFS5.0-EX-PA following test cases. UFS5.0 CTS covers both SCSI and Protocol tests covering all functionalities of the UFS5.0 Protocol. These 200 plus test cases can be run in a click of button different rate and test reports can be generated for records.

PGY-UFS5.0-EX-PA automatically runs Unipro 2.0 CTS test cases and Analysis the test cases and analysis the test result and provide pass/fail test results. Following test cases are supported in PGY-UFS5.0-EX-PA following test cases.

UniPro2.0 Conformance Test Suite supports UnIPro 2.0 CTS as per MIPI Alliance Specification.
User can select all PHY Adapter Layer tests, Data Link Layer Related Tests, Network Layer Related Tests, Transport layer related tests and SME related tests. Based on user selection will be run and results are displayed with pass/fail criteria. User can analyzer test results for failure condition of by reviewing the protocol decoded data.
User can use the drop menu to select the specific test case and run it and view the results.

PGY-UFS4-PA with UFS4 tester board and the software provides industry best custom UniPro and UFS5.0 Test case development platform for UFS3.1/4.0 devices. User can set the prepare time, sync length, burst speed, fast or fast auto mode, one lane or two-lane configuration. User can easily define each of the attributes of the UniPro or UFS5.0 packets. All these test cases can be saved and recalled for future use.

Test report of UniPro CTS, UFS 4.0 CTS and Custom test cases can be generated in mht format.

PGY-UFS5.0-EX-PA Software which provides additional views to write the UFS5.0 test cases, as well as ready to use UFS5.0 CTS and UniPro 2.0/3.0 CTS. User can write easily use Prodigy developed scripting language which self-guiding the user to write the script at ease. By selecting the UFS5.0 CTS and UniPro CTS in ‘viewʼ menu of PGY-UFS5.0-EX-PA software user can easily access the Conformance Test Suite and run it press of a single button.

PGY-UFS5.0-EX-PA optionally configured as a UFS5.0 device emulator to enable the testing of UFS5.0 host testing purpose. User
can to do the single stepping of Protocol command and UFS5.0 device emulator provides expected response to the command.
The response is preprogrammed through the host computer. This provides the flexibility to change UFS5.0 prepare, sync, filler
for any given packet. PGY-UFS5.0-PA supports FPGA Transceivers as a Physical layer.

UFS4/5 Host Under development can send specific traffic to PGY-UFS5.0-EX-PA. It will respond with Preprogrammed response to the Host protocol Packet. Design and test engineers can analysis the host response to device Emulator.

PGY-UFS5.0-EX-PA UFS5.0 Protocol Exerciser and Analyzer offers multiple probing solutions to meet the needs of different
devices under test. On certain UFS5.0 validation platforms, the protocol analyzer probes UFS5.0/M-PHY6.0 signals between the
host and device using a Board-to-Board interposer.
The M-PHY signals are actively split within the interposer:

• One copy continues between the host and device.
• The other copy is routed to the UFS5.0 Protocol Analyzer for decoding and analysis.

Prodigy Technovations also offers a complete range of UFS5.0 probing solutions, including:

• Solder-down probes
• Active power divider interposers
• Board-to-Board interposers
• UFS5.0 host validation boards

These interposers feature SMPM connectors for simple, reliable connectivity to the protocol analyzer

PGY-UFS5.0-EX-PA Protocol Analyzer Software
A Advanced Multi-Layer UFS5.0 Analysis

• Runs seamlessly on Windows OS.
• Connects to the PGY-UFS5.0-EX-PA hardware unit via USB 3.0.
• Provides intuitive configuration of both the protocol analyzer and the Board-to-Board interposer for reliable data capture.
• Powerful trigger capabilities ensure specific data capture, enabling quick debug and reduced development time.

Comprehensive Protocol Decoding

Decodes protocol activity across multiple layers:

• M-PHY
• PACP
• UniPro
• UFS5.0 (including TFS packets)

The UFS5.0 Protocol Analysis software delivers best-in-class correlation between UFS, UniPro, and M-PHY layers. Time
correlation across layers significantly reduces debug cycles, helping engineers quickly pinpoint issues and validate designs with
confidence.The high-performance decoding engine simplifies analysis of gigabytes of protocol information, making complex
debug tasks straightforward.The PGY-UFS5.0-EX-PA software combines powerful decoding, layer correlation, and multi-monitor
flexibility, enabling engineers to accelerate validation and streamline UFS5.0 protocol analysis.