Protocol Exercisers & Analyzers

SMBus Protocol Exerciser and Analyzer

Model No: PGY-SMBus-EX-PD

SMBus Protocol Exerciser and Analyzer (PGY-SMBus-EX-PD) is the Protocol Analyzer with multiple features to capture and debug communication between the host and the design under test. PGY-SMBus-EX-PD is the leading instrument that enables the design and test engineers to test the respective SMBus designs for their specifications by configuring the PGY-SMBus-EX-PD as Master/Slave, generating SMBus traffic, and decoding the SMBus protocol decode packets.

SMBus (System Management Bus) is one of the known low-speed serial protocols widely used for communication between various components in computer systems such as motherboards, batteries, temperature sensors, power management devices, sideband communication in PCIe, etc.

PGY-SMBus-EX-PD is the leading SMBus Protocol exerciser and analyzer that enables the design and test engineers to test their SMBus designs against SMBus specifications by configuring PGY-SMBus-EX-PD as master/slave, generating SMBus traffic with error injection capability and decoding SMBus Protocol packets.

Key Protocols
  • SMBus
  • Free Online Technical SupportFree Online Technical Support
  • Free Software UpdatesFree Software Updates
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  • Evaluation Units AvailableEvaluation Units Available
  • Key Features
  • Specifications
  • Supports SMBus protocol (version 3.2) and speeds up to 3.4 Mbps.
  • Configure it as Master or Slave. Can work Standalone with internal Master and Slaves (up to 3).
  • Supports all SMBus protocols like Quick Command, Send Byte, Receive Byte, Write Byte / Word, Read Byte/Word, Write 32, Read 32, Write 64, Read
  • 64, Block Write, Block Read, Process Call, Host notify, etc.
  • Support for Address Resolution Protocol (ARP)
  • Ability to generate and receive packets with (or) without PEC (Packet Error Checking) byte.
  • Supports Clock stretching at the slave end.
  • Simultaneously generate SMBus traffic and Protocol decode of the Bus.
  • Ability to configure the bus voltage level from 1V to 3.3V insteps of 50mV.
  • Can define parameters like setup time before repeat start, stop, clock after start, clock to data, etc.
  • Support script to execute the same set of commands multiple times (Loop Feature)
  • Continuous streaming of protocol data to the host computer to provide a large buffer.
  • Timing diagram of Protocol decoded bus.
  • Error Analysis in Protocol Decode
  • USB 2.0/3.0 host computer interface.
  • ​​API support for automation in Python or C++.
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Exerciser

PGY-SMBus-EX-PD supports SMBus traffic generation using GUI and Script. Users can generate simple SMBus using the GUI to test the DUT (Device Under Test). Script-based GUI provides flexibility to emulate the complete expected traffic in the real world including error injections. The script in Figure 4 generates SMBus traffic with the Write 32 command. The comments are included in the script.

Multi-Domain view

Multi-Domain View as in Figure 1 provides the complete view of SMBus Protocol activity in a single GUI. Users can easily set up the analyzer to generate SMBus traffic using the GUI or script. Users can set different trigger conditions from the setup menu to capture Protocol activity at specific events and decode the transition between Master and Slave. The decoded results can be viewed in the timing diagram and Protocol listing window with autocorrelation. This comprehensive view of information makes it the industry’s best, offering an easy-to-use solution to debug the SMBus protocol activity.

Timing Diagram and Protocol Listing View

The timing view provides the plot of SCL and SDA signals with a bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in the timing diagram for any timing errors.

The protocol window provides the decoded packet information in each state and all packet details with error info in a packet. The selected frame in the Protocol listing window will be autocorrelated in the timing view to view the timing information of the packet.

Powerful Trigger Capabilities

PGY-SMBus-EX-PD supports Auto, simple, and advanced trigger capabilities. The analyzer can trigger on any of the SMBus Protocol packets. Advanced Trigger provides the flexibility to monitor Multiple trigger conditions and can set multiple state trigger machines.

SMBus Protocol Exerciser & Analyzer Specifications

FeatureDetails
Exerciser:
No. of Master and SlavesConfigurable 1 Master + 3 Slaves
SMBCLK Frequency1KHz to 3.4MHz
Voltage Drive Level1V to 3.3V in steps of 50mV
SMBCLK Duty Cycle variationUser-Defined (10%-90%)
Timing ParametersUser configurable timing parameters using scripts (in steps of 5ns):
• tCAS: Clock delay after Start condition (min: 5ns)
• tCO: Clock in to data out delay (min: 5ns)
• tSU_STA: Setup time for repeated START (min: 10ns)
• tSU:STO: Setup time for STOP (min: 10ns)
• tSU:DAT: Setup time for Data (min: 10ns)
Delay between two messagesUser-Defined; Supports 3 resolution in µs/ms/s (min: 1µs)
Error InjectionACK/NACK Errors
Packet Error Checking (PEC)Option to generate and receive SMBus packets with (or) without PEC byte.
Clock StretchingSupported at the Slave end
SMBus Traffic GenerationCustom SMBus traffic generation using GUI and scripts
Command ScriptsReadily available command scripts that support all SMBus protocols.
API SupportSupport for Automation of operation in Python or C++.
Protocol Analysis:
Protocol DecodeAs per SMBus version 3.2
Protocol Views• Timing diagram view.
• Protocol listing view.
• Bus-Diagram to display protocol packets with timing diagram plot.
• Cursor support for time measurement.
• Marker support between messages for time measurement.
Protocol Trigger• Auto (Trigger on any packet).
• Simple (Trigger on user defined SMBus packet).
• Advanced (Multistate & Multilevel trigger with timer capability).
Protocol Error Report• ACK/NACK Errors.
• Non-standard Frames.
• Error in PEC byte.
Capture DurationContinuous streaming of protocol data to host HDD/SSD
Host ConnectivityUSB 3.0 / 2.0 interface

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