The System Power Management Interface, or SPMI, enables communication between power controllers and power management devices in mobile, automotive and other SoC-based systems. Its multi-controller, multi-target architecture, bus arbitration process and target-initiated communication can introduce complex validation and debugging challenges.
This webinar provides a practical overview of SPMI protocol operation and demonstrates how engineers can validate controller and target implementations using traffic generation, protocol analysis, error injection and compliance testing.
The session will cover SPMI bus architecture, command sequences, arbitration, frame structure, acknowledgement, parity and timing behavior. A live demonstration of the PGY-SPMI-EX-PD Protocol Exerciser and Analyzer will show how to emulate controllers and targets, generate protocol traffic, inject errors, vary timing parameters, trigger on specific events and analyze decoded results.
Agenda
- SPMI protocol overview
- Two-wire SPMI bus architecture
- Controllers, targets and device addressing
- SPMI 1.0 and 2.0 overview
- SPMI protocol operation
- Sequence Start Condition
- Command, address and data frames
- ACK/NACK, parity and bus park cycles
- Bus arbitration and target communication
- Multi-controller arbitration
- A Bit and SR Bit arbitration
- Request-capable and non-request-capable targets
- Bus initialization and controller connection
- Common SPMI validation challenges
- Capturing specific protocol events
- Debugging continuous bus traffic
- Validating timing and voltage margins
- Detecting protocol and signal integrity errors
- Live demonstration using PGY-SPMI-EX-PD
- Controller and target emulation
- SPMI traffic generation
- Protocol decode and timing analysis
- Advanced triggering
- Parity and glitch error injection
- Frequency, voltage, duty cycle and TCO variation
- PICS compliance testing and report generation
